View source for Burroughs MCP Architecture

''[[:en:Burroughs large systems|<span style="color: pink;">EnWiki Version</span>]]''

== Dominion Preface ==

Noting that by 2012-08 the Lede at least at the English wiki was better, more accurate. I put a lot into the article that's still there, the illustration for example, the characteristics, the point about re-entrancy. I don't expect to maintain the below, but I just learned about the B205 and apparently my long presumption that Burroughs didn't have computers  in the '50s is only partially true. They just didn't make any themselves, the B205 (1956) was made by a company Burroughs purchased and rebranded as their product. 

== Content ==

Founded in the 1880s, Burroughs was the oldest continuously operating entity in computing, but by the late 1950s its computing equipment was still limited to electromechanical [[Accounting Machine|accounting machines]] such as the [[Burroughs Sensimatic|Sensimatic]]; as such it had nothing to compete with its traditional rivals [[IBM]] and [[NCR Corporation|NCR]] who had started to produce larger-scale computers, or with recently-founded [[Univac]]. The first machine, the B5000, was designed in 1961 and Burroughs sought to address its late entry in the market with the strategy of a completely different design based on the most advanced computing ideas available at the time. While the B5000 architecture is dead, it inspired the B6500, and computers using that architecture are still in production as the [[Unisys]] ClearPath MCP machines. The third and largest line<ref name=Da8500/><ref name=Ga8500/> was a dead end. In addition to the proprietary [[CMOS]] architecture, Unisys also uses Intel [[Xeon]] processors, and runs [[Burroughs MCP|MCP]], [[Microsoft Windows]] and [[Linux]] operating systems on their servers.

In the 1970s, [[Burroughs Corporation]] was organized into three divisions with very different product line architectures for high-end, mid-range, and entry-level business computer systems.  Each division's product line grew from a different [[Robert (Bob) Barton]] concept for how to optimize a computer's instruction set for particular programming languages.
The '''Burroughs Large Systems Group''' designed large mainframes using '''stack machine''' instruction sets with dense 12-bit instructions and 48-bit data words.  The first such design was the B5000 in 1961.  It was optimized for running [[ALGOL 60]] extremely well, using simple compilers.  It evolved into the B5500.  Subsequent major redesigns include the B6500 line and its successors, and the separate B8500 line.  'Burroughs Large Systems' referred to all of these product lines together, in contrast to the [[COBOL]]-optimized [[Burroughs B2500|Medium Systems]] or the flexible-architecture [[B1700|Small Systems]] all of which ran versions of the MCP. 
[[Image:b6700.jpg|thumb|420px|right|Figure 4.5 From the ACM Monograph in the References. ''[[Elliot Organick]] 1973.'']]
{{TOCleft}}
==B5000==
The first member of the first series, the B5000,<ref name=B5000-21005/> was designed beginning in 1961 by a team under the leadership of [[:en:Robert S. Barton]]. It was a unique machine, well ahead of its time. It has been listed by the influential computing scientist [[John Mashey]] as one of the architectures that he admires the most. "I always thought it was one of the most innovative examples of combined hardware/software design I've seen, and far ahead of its time."<ref name=johnmashey>
{{cite newsgroup
| title = Admired designs / designs to study
| author = John Mashey
| date = 2006-08-15
| newsgroup = comp.arch
| id = 1155671202.964792.162180@b28g2000cwb.googlegroups.com
| url = http://groups.google.com/group/comp.arch/msg/8dcee778af867966
| accessdate=2007-12-15
}}</ref> The B5000 was succeeded by the B5500<ref name=B1021326/> and B5700. While there was no successor to the B5700, the B5000 line heavily influenced the design of the B6500, and Burroughs ported the [[Burroughs MCP|Master Control Program]] ('''MCP''') to that machine.

===Unique features===
* All code automatically [[Reentrant (subroutine)|reentrant]] (fig 4.5 from the ACM Monograph shows [[zero address arithmetic|in a nutshell]] why): programmers don't have to do anything more to have any code in any language spread across processors than to use just the two shown simple primitives. This is perhaps the canonical but no means the only benefit of the these major distinguishing features of this architecture:
** Partially data-driven [[Tagged architecture|tagged]] and descriptor-based architecture
** Hardware was designed to support software requirements
** Hardware designed to exclusively support [[High-level programming language|high-level]] [[programming languages]]
** No [[Assembly language]] or assembler; all system software written in an extended variety of [[ALGOL]]. However, [[ESPOL]] had statements for each of the syllables in the architecture.
** Few programmer accessible registers
** Simplified [[instruction set]]
** Stack architecture (to support high-level algorithmic languages)
** Support for high-level [[operating system]] (MCP, [[MCP (Burroughs Large Systems)|Master Control Program]])

* Support for master/slave multiprocessing
* Support for other languages such as [[COBOL]]
* Powerful string manipulation
* An attempt at a secure architecture prohibiting unauthorized access of data or disruptions to operations<ref group=NB>There were security issues</ref>
* Early error-detection supporting development and testing of software
* First commercial implementation of virtual memory<ref group=NB>Unless you counted the [[Ferranti]] [[Atlas Computer (Manchester)|Atlas]] as a commercial machine.</ref>
* Successors still exist in the [[Unisys]] ClearPath/MCP machines
* Influenced many of today's computing techniques


====Unique system design====
The B5000 was revolutionary at the time in that the architecture and instruction set were designed with the needs of software taken into consideration. This was a large departure from the computer system design of the time, where a processor and its instruction set would be designed and then handed over to the software people, and is still. That is, modern architectures such as [[x86 architecture|x86]] or [[PowerPC|PPC]] are essentially traditional instruction set based architectures rather than holistic designs like the original Burroughs systems.

====Language support====
The B5000 was designed to exclusively support high-level languages. This was at a time when such languages were just coming to prominence with [[FORTRAN]] and then [[COBOL]]. FORTRAN and COBOL were considered weaker languages by some, when it comes to modern software techniques, so a newer, mostly untried language was adopted, [[Algol 60|ALGOL-60]]. The ALGOL dialect chosen for the B5000 was [[Elliott ALGOL]], first designed and implemented by [[C. A. R. Hoare|C.A.R. Hoare]] on an Elliot 503. This was a practical extension of ALGOL with IO instructions (which ALGOL had ignored) and powerful string processing instructions.
Hoare's famous [[Turing Award]] lecture was on this subject.

Thus the B5000 was based on a very powerful language. Most other vendors could only dream of implementing an ALGOL compiler and most in the industry dismissed ALGOL as being unimplementable. However, a bright young student named [[Donald Knuth]] had previously implemented ALGOL-58 on an earlier Burroughs machine during the three months of his summer break. Many wrote ALGOL off, mistakenly believing that high-level languages could not have the same power as assembler, and thus not realizing ALGOL's potential as a systems programming language.

The Burroughs ALGOL compiler was very fast &mdash; this impressed the Dutch scientist [[Edsger Dijkstra]] when he submitted a program to be compiled at the B5000 Pasadena plant. His deck of cards was compiled almost immediately and he immediately wanted several machines for his university, [[Eindhoven University of Technology]] in the Netherlands. The compiler was fast for several reasons, but the primary reason was that it was a [[one-pass compiler]]. Early computers did not have enough memory to store the source code, so compilers (and even assemblers) usually needed to read the source code more than once. The Burroughs ALGOL syntax, unlike the official language, requires that each variable (or other object) be declared before it is used, so it is feasible to write an ALGOL compiler that reads the data only once. This concept has profound theoretical implications, but it also permits very fast compiling. Burroughs large systems could compile as fast as they could read the source code from the [[punched card]]s, and they had the fastest card readers in the industry.

The powerful Burroughs COBOL compiler was also a one-pass compiler and equally fast. A 4000-card COBOL program compiled as fast as the 1000-card/minute readers could read the code. The program was ready to use as soon as the cards went through the reader.

==B6500==

The B6500 and B7500 were the first computers in the only Burroughs system to survive to the present day. While they were inspired by the B5000, they had a totally new architecture. Among the most important differences were
*The B6500 had variable length instructions with an 8-bit syllable instead of fixed length instructions with a 12-bit syllable.
*The B6500 had a 51-bit<ref group=NB>Not counting error controls</ref> instead of a 48-bit word, and used 3 bits as a [[Tagged architecture|tag]]
*The B6500 had [[Symmetric multiprocessing|Symmetric Multiprocessing (SMP)]]
*The B6500 had a [[Spaghetti stack|Saguaro stack]]
*The B6500 had paged arrays
*The B6500 had a ''Display'' to allow nested subroutines to access variables in outer blocks.

==B8500==
The B8500<ref name=Da8500/><ref name=Ga8500/> line derives from the D825,<ref>{{cite book
 | title=Proceedings of the December 4–6, 1962, Fall Joint Computer Conference
 | chapter=D825 - a multiple-computer system for command & control
 | first1 = James P.
 | last1  = Anderson
 | first2 = Samuel A.
 | last2  = Hoffman
 | first3 = Joseph
 | last3  = Shifman
 | first4 = Robert J.
 | last4  = Williams
 | series=AFIPS Conference Proceedings
 | volume = Volume 24
 | year=1962
 | doi=10.1145/1461518.1461527
 | separator = ,}}</ref> a military computer that was inspired by the B5000.

==History==
{{Expand section|date=June 2008}} <!-- please see the discussion page. I'm attempting to build a table to add to this, but I need help.-->
The first of the Burroughs large systems was the B5000. Designed in 1961, it was a second-generation computer using [[Discrete device|discrete transistor]] logic and [[magnetic core memory]]. The successor machines followed the hardware development trends to re-implement the architecture in new logic over the next 25 years, with the B5500, B6500, B5700, B6700, B7700, B6800, B7800, and finally the Burroughs A series. After a merger in which Burroughs acquired [[Sperry Corporation]] and changed its name to [[Unisys]], the company continued to develop new machines based on the '''MCP [[CMOS]]''' [[ASIC]]. These machines were the Libra 100 through the Libra 500, With the Libra 590 being announced in 2005. Later Libras, including the 590, also incorporate Intel Xeon processors and can run the Burroughs large systems architecture in emulation as well as on the MCP CMOS processors. It is unclear if Unisys will continue development of new MCP CMOS ASICs.

{| class="wikitable" cellpadding="0" cellspacing="0" width="600" align="center"
! style="background: #017A5B;" cellpadding="2" colspan="4" |{{color|white|Burroughs (1961–1986)}}
|- text-align="left"
| '''B5000'''|| 1961 || initial system, 2nd generation (transistor) computer
|-
| '''B5500'''|| 1964 || 3x speed improvement(?)<ref>[http://www.cc.gatech.edu/gvu/people/randy.carpenter/folklore/v3n5.html Burroughs 3rd Generation.]</ref>
|-
| '''B6500'''|| 1969 || 3rd gen computer (integrated circuits), up to 4 processors
|-
| '''B5700'''|| 1971 || new name for B5500{{Disputed-inline|Talk:Burroughs large systems# Are x700 new names for old products or names for new products|reason=conflicts with sources|date=November 2010}}
|-
| '''B6700'''|| 1971 || new name/bug fix for B6500{{Disputed-inline|Talk:Burroughs large systems# Are x700 new names for old products or names for new products|reason=conflicts with sources|date=November 2010}}
|-
| '''B7700'''|| 1972 || faster processor, cache for stack, up to 8 processors.
|-
| '''B6800'''|| 1977? || semiconductor memory, [[Non-Uniform Memory Access|NUMA]] architecture
|-
| '''B7800'''|| 1977? || semiconductor memory, faster, up to 16? processors
|-
| '''A Series'''|| 1984 || Re-implemented in custom-designed Motorola [[Emitter-coupled logic|ECL]] MCA1, then MCA2 [[gate array]]s
|-
! style="background: #017A5B;" cellpadding="2" colspan="4" |{{color|white|Unisys (1986–present))}}
|-
| '''Micro A'''|| 1989 || desktop "mainframe" with single-chip SCAMP<ref>[http://www.classiccmp.org/dunfield/other/h/uascpu.jpg SCAMP picture at dave's Old computers]</ref><ref>{{Citation|last=Reitman|first=Valerie|title=Unisys Ready To Offer A Desktop Mainframe|date=January 18, 1989|newspaper=[[Philadelphia Inquirer]]|url=http://articles.philly.com/1989-01-18/business/26123789_1_unisys-scamp-mainframe|accessdate=2011-04-16}}</ref> processor.
|-
| '''Clearpath HMP NX 4000''' || 198? || ??
|-
| '''Clearpath HMP NX 5000''' || 199? || ??
|-
| '''Clearpath HMP LX 5000''' || 1998 || Implements Burroughs Large systems in emulation only ([[Xeon]] processors)<ref>[http://www.highbeam.com/doc/1G1-50063166.html Unisys Accelerates Mainframe Rebirth with New ClearPath Enterprise Servers, Aggressive New Pricing. - Business Wire - HighBeam Research<!-- Bot generated title -->]</ref>
|-
| '''Libra 100''' || 2002? || ??
|-
| '''Libra 200''' || 200? || ??
|-
| '''Libra 300''' || 200? || ??
|-
| '''Libra 400''' || 200? || ??
|-
| '''Libra 500''' || 2005? || e.g. Libra 595<ref>[http://www.unisys.com/products/mainframes/mcp__mainframes/earlier__mcp__models.htm Libra 595]</ref>
|-
| '''Libra 600''' || 2006? || ??
|}

==Primary Lines==
Hardware and software design, development, and manufacturing were split between two primary locations, in [[Orange County, California]], and the outskirts of [[Philadelphia]].  The Orange County location, which centered around a plant in [[Mission Viejo, California]] but at times included facilities in nearby [[Irvine, California|Irvine]] and [[Lake Forest, California|Lake Forest]], was responsible for the smaller B6x00 line, while the East Coast operations, centered around [[Tredyffrin, Pennsylvania]], handled the larger B7x00 line.  All machines from both lines were fully object-compatible, meaning a program compiled on one could be executed on another.  Newer and larger models had instructions which were not supported on older and slower models, but the hardware, when encountering an unrecognized instruction, invoked an operating system function which interpreted it.  Other differences include how process switching and I/O were handled, and maintenance and cold-starting functionality.  Larger systems included hardware process scheduling and more capable input/output modules, and more highly-functional maintenance processors.  When the Bxx00 models were replaced by the A Series models, the differences were retained but no longer readily identifiable by model number.

==ALGOL==
{{Main|ALGOL}}
{{Merge from|Elliott ALGOL|discuss=Talk:Elliott_ALGOL#Merge_proposal|date=May 2009}}

The Burroughs large systems implement an ALGOL-derived [[stack architecture]], unlike linear architectures such as [[PDP-11]], [[68k|Motorola M68k]], and [[Itanium]] or segmented architectures such as [[x86]] and [[Texas Instruments]]. (This refers to the layout of the memory and how a program uses it.)

While B5000 was designed specifically around ALGOL, this was only a starting point. Other business-oriented languages such as COBOL were also well supported, most notably by the powerful string operators which were included for the development of fast compilers.

The ALGOL used on the B5000 is an extended ALGOL subset. It includes powerful string manipulation instructions but excludes certain ALGOL constructs, notably unspecified formal parameters. A DEFINE mechanism serves a similar purpose to the [[C preprocessor|#defines]] found in C, but is fully integrated into the language rather than being a preprocessor. The EVENT data type facilitates coordination between processes, and ON FAULT blocks enable handling program faults.

The user level of ALGOL does not include many of the insecure constructs needed by the operating system and other system software. Two levels of language extensions provide the additional constructs: ESPOL and NEWP for writing the MCP and closely related software, and DCALGOL and DMALGOL to provide more specific extensions for specific kinds of system software.

===ESPOL and NEWP===
Originally, the B5000 MCP operating system was written in an extension of extended ALGOL called ESPOL (Executive Systems Programming Oriented Language). This was replaced in the mid-to-late 70s by a language called NEWP. Though NEWP probably just meant "New Programming language", legends surround the name. A common (perhaps apocryphal) story around Burroughs at the time suggested it came from “''No Executive Washroom Privileges''.” Another story is that circa 1976, John McClintock of Burroughs (the software engineer developing NEWP) named the language "NEWP" after being asked, yet again, "does it have a name yet": answering "nyoooop", he adopted that as a name. NEWP, too, was a subset ALGOL extension, but it was more secure than ESPOL, and dropped some little-used complexities of ALGOL. In fact, all unsafe constructs are rejected by the NEWP compiler unless a block is specifically marked to allow those instructions. Such marking of blocks provide a multi-level protection mechanism.

NEWP programs that contain unsafe constructs are initially non-executable. The security administrator of a system is able to "bless" such programs and make them executable, but normal users are not able to do this. (Even "privileged users", who normally have essentially root privilege, may be unable to do this depending on the configuration chosen by the site.) While NEWP can be used to write general programs and has a number of features designed for large software projects, it does not support everything ALGOL does.

NEWP has a number of facilities to enable large-scale software projects, such as the operating system, including named interfaces (functions and data), groups of interfaces, modules, and super-modules. Modules group data and functions together, allowing easy access to the data as global within the module. Interfaces allow a module to import and export functions and data. Super-modules allow modules to be grouped.

===DCALGOL and Message Control Systems (MCS)===
The second intermediate level of security between operating system code (in NEWP) and user programs (in ALGOL) is for middleware programs, which are written in DCALGOL (data comms ALGOL). This is used for message reception and dispatching which remove messages from input queues and places them on queues for other processes in the system to handle. Middleware such as COMS (introduced around 1984) receive messages from around the network and dispatch these messages to specific handling processes or to an MCS (Message Control System) such as CANDE ("'''C'''ommand '''AND E'''dit," the program development environment).

MCSs are items of software worth noting – they control user sessions and provide keeping track of user state without having to run per-user processes since a single MCS stack can be shared by many users. Load balancing can also be achieved at the MCS level. For example saying that you want to handle 30 users per stack, in which case if you have 31 to 60 users, you have two stacks, 61 to 90 users, three stacks, etc. This gives B5000 machines a great performance advantage in a server since you don't need to start up another user process and thus create a new stack each time a user attaches to the system. Thus you can efficiently service users (whether they require state or not) with MCSs. MCSs also provide the backbone of large-scale transaction processing.

The MCS talked with an external co-processor, the TCP (Terminal Control Processor). This was a 24-bit minicomputer with a conventional register architecture and hardware I/O capability to handle thousands of remote terminals. The TCP and the B6500 communicated by messages in memory, essentially packets in today's terms, and the MCS did the B6500-side processing of those messages. The TCP did have an assembler, but that assembler was the B6500 ALGOL compiler. There was one ALGOL function for each kind of TCP instruction, and if you called that function then the corresponding TCP instruction bits would be emitted to the output. A TCP program was an ALGOL program comprising nothing but a long list of calls on these functions, one for each assembly language statement. Essentially ALGOL acted like the macro pass of a macro assembler. The first pass was the ALGOL compiler; the second pass was running the resulting program (on the B6500) which would then emit the binary for the TCP.

===DMALGOL and databases===
Another variant of ALGOL is DMALGOL (Data Management ALGOL). DMALGOL is ALGOL extended for compiling the DMSII database software from database description files created by the DASDL compiler. Database designers and administrators compile database descriptions to generate DMALGOL code tailored for the tables and indexes specified. Administrators never need to write DMALGOL themselves. Normal user-level programs obtain database access by using code written in application languages, mainly ALGOL and COBOL, extended with database instructions and transaction processing directives. The most notable feature of DMALGOL is its preprocessing mechanisms to generate code for handling tables and indices.

DMALGOL preprocessing includes variables and loops, and can generate names based on compile-time variables. This enables tailoring far beyond what can be done by preprocessing facilities which lack loops.

DMALGOL is used to provide tailored access routines for [[Unisys DMSII|DMSII]] databases. After a database is defined using the Data Access and Structure Definition Language (DASDL), the schema is translated by the preprocessor into tailored DMALGOL access routines and then compiled.
This means that, unlike in other DBMS implementations, there is often no need for database-specific if/then/else code at run-time. In the 1970s, this "tailoring" was used very extensively to reduce the code footprint and execution time. It became much less used in later years, partly because low-level fine tuning for memory and speed became less critical, and partly because eliminating the preprocessing made coding simpler and thus enabled more important optimizations.

Roy Guck of Burroughs was one of the main developers of [[Unisys DMSII|DMSII]].

In later years, with compiler code size being less of a concern, most of the preprocessing constructs were made available in the user level of ALGOL. Only the unsafe constructs and the direct processing of the database description file remain restricted to DMALGOL.

==Stack architecture==
In many early systems and languages, programmers were often told not to make their routines too small.  Procedure calls and returns were expensive, because a number of operations had to be performed to maintain the stack. The B5000 was designed as a stack machine – all program data except for arrays (which include strings and objects) was kept on the stack. This meant that stack operations were optimized for efficiency. As a stack-oriented machine, there are no programmer addressable registers.

[[Computer multitasking|Multitasking]] is also very efficient on B5000 machines. There is one specific instruction to perform process switches – MVST (move stack).<ref>{{cite book
 | last = Organick
 | first = Elliot
 | authorlink = Elliot Organick
 | title = Computer System Organization
 | publisher = [[Association for Computing Machinery|ACM]]
 | year = 1973
 | pages = 115–117
 | isbn = 0125282508 }}</ref> Each stack represents a process (task or thread) and tasks can become blocked waiting on resource requests (which includes waiting for a processor to run on if the task has been interrupted because of preemptive multitasking). User programs cannot issue an MVST, and there is only one line of code in the operating system where this is done.

So a process switch proceeds something like this – a process requests a resource that is not immediately available, maybe a read of a record of a file from a block which is not currently in memory, or the system timer has triggered an interrupt. The operating system code is entered and run on top of the user stack. It turns off user process timers. The current process is placed in the appropriate queue for the resource being requested, or the ready queue waiting for the processor if this is a preemptive context switch. The operating system determines the first process in the ready queue and invokes the instruction move_stack, which makes the process at the head of the ready queue active.

===Stack speed and performance===
Some of the detractors of the B5000 architecture believed that stack architecture was inherently slow compared to register-based architectures. The trick to system speed is to keep data as close to the processor as possible. In the B5000 stack, this was done by assigning the top two positions of the stack to two registers A and B. Most operations are performed on those two top of stack positions. On faster machines past the B5000, more of the stack may be kept in registers or cache near the processor.

Thus the designers of the current B5000 systems can optimize in whatever is the latest technique, and programmers do not have to adjust their code for it to run faster – they do not even need to recompile, thus protecting software investment. Some programs have been known to run for years over many processor upgrades. Such speed up is limited on register-based machines.{{Citation needed|date=January 2010}}

Another point for speed as promoted by the RISC designers was that processor speed is considerably faster if everything is on a single chip. It was a valid point in the 1970s when more complex architectures such as the B5000 required too many transistors to fit on a single chip. However, this is not the case today and every B5000 successor machine now fits on a single chip as well as the performance support techniques such as caches and instruction pipelines.

In fact, the A Series line of B5000 successors included the first single chip mainframe, the Micro-A of the late 1980s. This "mainframe" chip (named SCAMP for Single-Chip A-series Mainframe Processor) sat on an Intel-based plug-in PC board.

=== How programs map to the stack architecture ===

Here is an example of how programs map to the stack architecture

 '''begin'''
    — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
    — This is lexical level 2 (level zero is reserved for the operating system and level 1 for code segments).
    — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
    
    — At level 2 we place global variables for our program.
    
    '''integer''' ''i'', ''j'', ''k''
    '''real''' ''f'', ''g''
    '''array''' ''a'' [0:9]
    
    '''procedure''' ''p'' ('''real''' ''p1'', ''p2'')
       '''value''' ''p1''     — p1 passed by value, p2 implicitly passed by reference.
       '''begin'''
          — — — — — — — — — — — — — — — — — —
          — This block is at lexical level 3
          — — — — — — — — — — — — — — — — — —
          '''real''' ''r1'', ''r2''<br />
          ''r2'' := ''p1'' * ''5''
          ''p2'' := ''r2''  — This sets 'g' to the value of r2
          ''p1'' := ''r2''  — This set 'p1' to r2, but not 'f'
          — Since this overwrites the original value of f in p1 it most likely indicates
          — an error. Few of ALGOL's successors have corrected this situation by
          — making value parameters read only – most have not.
          
          '''if''' ''r2'' > ''10'' '''then'''
             '''begin'''
                — — — — — — — — — — — — — — — — — — — — — — — — — — — —
                — A variable declared here makes this lexical level 4
                — — — — — — — — — — — — — — — — — — — — — — — — — — — —
                '''integer''' ''n''<br />
                — The declaration of a variable makes this a block, which will invoke some
                — stack building code. Normally you won't declare variables here, in which
                — case this would be a compound statement, not a block.
                
                ... <== sample stack is executing somewhere here.
             '''end'''
       '''end'''
       
    .....
    
    ''p'' (''f'', ''g'')
 '''end'''

Each stack frame corresponds to a lexical level in the current execution environment. As you can see, lexical level is the static textual nesting of a program, not the dynamic call nesting. The visibility rules of ALGOL, a language designed for single pass compilers, mean that only variables declared before the current position are visible at that part of the code except for forward declarations. All variables declared in enclosing blocks are visible. Another case is that variables of the same name may be declared in inner blocks and these effectively hide the outer variables which become inaccessible.

Since lexical nesting is static, it is very rare to find a program nested more than five levels deep, and it could be argued that such programs would be poorly structured. B5000 machines allow nesting of up to 32 levels. Procedures can be invoked in four ways – normal, call, process, and run.

=== Procedures ===

The normal invocation invokes a procedure in the normal way any language invokes a routine, by suspending the calling routine until the invoked procedure returns.

The '''call''' mechanism invokes a procedure as a coroutine. Coroutines have partner tasks, where control is explicitly passed between the tasks by means of a CONTINUE instruction. These are synchronous processes.

The '''process''' mechanism invokes a procedure as an asynchronous task and in this case a separate stack is set up starting at the lexical level of the processed procedure. As an asynchronous task, there is no control over exactly when control will be passed between the tasks, unlike coroutines. Note also that the processed procedure still has access to the enclosing environment and this is a very efficient IPC (Inter Process Communication) mechanism. Since two or more tasks now have access to common variables, the tasks must be synchronized to prevent race conditions, which is handled by the EVENT data type, where processes can WAIT on an event until they are caused by another cooperating process. EVENTs also allow for mutual exclusion synchronization through the PROCURE and LIBERATE functions. If for any reason the child task dies, the calling task can continue – however, if the parent process dies, then all child processes are automatically terminated. On a machine with more than one processor, the processes may run simultaneously. This EVENT mechanism is a basic enabler for multiprocessing in addition to multitasking.

==== Run invocation type ====

The last invocation type is '''run'''. This runs a procedure as an independent task which can continue on after the originating process terminates. For this reason, the child process cannot access variables in the parent's environment, and all parameters passed to the invoked procedure must be call-by-value.

Thus Burroughs Extended ALGOL had some of the multi-processing and synchronization features of later languages like Ada, with the added benefit that support for asynchronous processes was built into the hardware level.

==== Inline procedures ====

One last possibility is that a procedure may be declared INLINE, that is when the compiler sees a reference to it the code for the procedure is generated inline to save the overhead of a procedure call. This is best done for small pieces of code and is like a define, except you don't get the problems with parameters that you can with defines. This facility is available in NEWP.

==== Asynchronous calls ====

In the example program only normal calls are used, so all the information will be on a single stack. For asynchronous calls, the stack would be split into multiple stacks so that the processes share data but run asynchronously.

==== Display registers ====

A stack hardware optimization is the provision of D (or "display") registers. These are registers that point to the start of each called stack frame. These registers are updated automatically as procedures are entered and exited and are not accessible by any software. There are 32 D registers, which is what limits to 32 levels of lexical nesting.

Consider how we would access a lexical level 2 (D[2]) global variable from lexical level 5 (D[5]). Suppose the variable is 6 words away from the base of lexical level 2. It is thus represented by the address couple (2, 6). If we don't have D registers, we have to look at the control word at the base of the D[5] frame, which points to the frame containing the D[4] environment. We then look at the control word at the base of this environment to find the D[3] environment, and continue in this fashion until we have followed all the links back to the required lexical level. Note this is not the same path as the return path back through the procedures which have been called in order to get to this point. (The architecture keeps both the data stack and the call stack in the same structure, but uses control words to tell them apart.)

As you can see, this is quite inefficient just to access a variable. With D registers, the D[2] register points at the base of the lexical level 2 environment, and all we need to do to generate the address of the variable is to add its offset from the stack frame base to the frame base address in the D register. (There is an efficient linked list search operator LLLU, which could search the stack in the above fashion, but the D register approach is still going to be faster.) With D registers, access to entities in outer and global environments is just as efficient as local variable access.

 D Tag Data                — Comments
 register

 | 0        | ''n''          | — The integer 'n' address couple (4, 1)
 |-----------------------|
 | D[4]==>3 | '''MSCW'''       | — The Mark Stack Control Word containing the link to D[3].
 |=======================|
 | 0        | ''r2''         | — The real 'r2' address couple (3, 5)
 |-----------------------|
 | 0        | ''r1''         | — The real 'r1' address couple (3, 4)
 |-----------------------|
 | 1        | ''p2''         | — An SIRW reference to 'g' at (2,6)
 |-----------------------|
 | 0        | ''p1''         | — The parameter 'p1' from value of 'f' address couple (3, 2)
 |-----------------------|
 | 3        | '''RCW'''        | — A return control word
 |-----------------------|
 | D[3]==>3 | '''MSCW'''       | — The Mark Stack Control Word containing the link to D[2].
 |=======================| — The array 'a' address couple (2, 7)
 | 1        | ''a''          | ====================>[ten word memory block]
 |-----------------------|
 | 0        | ''g''          | — The real 'g' address couple (2, 6)
 |-----------------------|
 | 0        | ''f''          | — The real 'f' address couple (2, 5)
 |-----------------------|
 | 0        | ''k''          | — The integer 'k' address couple (2, 4)
 |-----------------------|
 | 0        | ''j''          | — The integer 'j' address couple (2, 3)
 |-----------------------|
 | 0        | ''i''          | — The integer 'i' address couple (2, 2)
 |-----------------------|
 | 3        | '''RCW'''        | — A return control word
 |-----------------------|
 | D[2]==>3 | '''MSCW'''       | — The Mark Stack Control Word containing the link to the previous stack frame.
 |=======================| — Stack bottom

If we had invoked the procedure p as a coroutine, or a process instruction, the D[3] environment would have become a separate D[3]-based stack. Note that this means that asynchronous processes still have access to the D[2] environment as implied in ALGOL program code. Taking this one step further, a totally different program could call another program’s code, creating a D[3] stack frame pointing to another process’ D[2] environment on top of its own process stack. At an instant the whole address space from the code’s execution environment changes, making the D[2] environment on the own process stack not directly addressable and instead make the D[2] environment in another process stack directly addressable. This is how library calls are implemented. At such a cross-stack call, the calling code and called code could even originate from programs written in different source languages and be compiled by different compilers.

Note that the D[1] and D[0] environments do not occur in the current process's stack. The D[1] environment is the code segment dictionary, which is shared by all processes running the same code. The D[0] environment represents entities exported by the operating system.

Stack frames actually don’t even have to exist in a process stack. This feature was used early on for file IO optimization, the FIB (file information block) was linked into the display registers at D[1] during IO operations. In the early nineties, this ability was implemented as a language feature as STRUCTURE BLOCKs and – combined with library technology - as CONNECTION BLOCKs. The ability to link a data structure into the display register address scope implemented object orientation. Thus, the B5000 actually used a form of object orientation long before the term was ever used.

=== Stack structure advantages ===

One nice thing about the stack structure is that if a program does happen to fail, a stack dump is taken and it is very easy for a programmer to find out exactly what the state of a running program was. Compare that to core dumps and exchange packages of other systems.

Another thing about the stack structure is that programs are implicitly recursive. FORTRAN was not a recursive language and perhaps one stumbling block to people's understanding of how ALGOL was to be implemented was how to implement recursion. On the B5000, this was not a problem – in fact, they had the reverse problem, how to stop programs from being recursive. In the end they didn't bother, even the Burroughs FORTRAN compiler was recursive, since it was unproductive to stop it being so.

Thus Burroughs FORTRAN was better than any other implementation of FORTRAN.{{Citation needed|date=February 2007}} In fact, Burroughs became known for its superior compilers and implementation of languages, including the object-oriented [[Simula]] (a superset of ALGOL), and [[Kenneth E. Iverson|Iverson]], the designer of [[APL (programming language)|APL]] declared that the Burroughs implementation of APL was the best he'd seen.{{Citation needed|date=February 2007}} [[John McCarthy (computer scientist)|John McCarthy]], the language designer of [[LISP]] disagreed, since LISP was based on modifiable code{{Citation needed|date=February 2007}}, he did not like the unmodifiable code of the B5000{{Citation needed|date=February 2007}}, but most LISP implementations would run in an interpretive environment anyway.

Note also that stacks automatically used as much memory as was needed by a process. There was no having to do SYSGENs on Burroughs systems as with competing systems in order to preconfigure memory partitions in which to run tasks.

==Tagged architecture==
The most defining aspect of the B5000 is that it is a stack machine as treated above. However, two other very important features of the architecture is that it is [[tagged architecture|tag-based]] and descriptor-based.

In the original B5000, a flag bit in each control or numeric word<ref>There was no flag bit in words containing character data or code</ref> was set aside to identify the word as a control word or numeric word. This was partially a security mechanism to stop programs from being able to corrupt control words on the stack.

Later, when the B6500 was designed, it was realized that the 1-bit control word/numeric distinction was a powerful idea and this was extended to three bits outside of the 48 bit word into a tag. The data bits are bits 0-47 and the tag is in bits 48-50. Bit 48 was the read-only bit, thus odd tags indicated control words that could not be written by a user-level program. Code words were given tag 3. Here is a list of the tags and their function:

{|class="wikitable"
|-
!Tag!!Word kind!!Description
|-
|0||Data||All kinds of user and system data (text data and single precision numbers)
|-
|2||Double||Double Precision data
|-
|4||SIW||Step Index word (used in loops)
|-
|6|| ||Uninitialized data
|-
| ||SCW||Software Control Word (used to cut back the stack)
|-
|1||IRW||Indirect Reference Word
|-
| ||SIRW||Stuffed Indirect Reference Word
|-
|3||Code||Program code word
|-
| ||MSCW||Mark Stack Control Word
|-
| ||RCW||Return Control Word
|-
| ||TOSCW||Top of Stack Control Word
|-
| ||SD||Segment Descriptor
|-
|5||Descriptor||Data block descriptors
|-
|7||PCW||Program Control Word
|}

Note: Internally, some of the machines had 60 bit words, with the extra bits being used for engineering purposes such as a [[Hamming code]] error-correction field, but these were never seen by programmers.

Note: The current incarnation of these machines, the Unisys ClearPath has extended tags further into a four bit tag. The microcode level that specified four bit tags was referred to as level Gamma.

Even-tagged words are user data which can be modified by a user program as user state. Odd-tagged words are created and used directly by the hardware and represent a program's execution state. Since these words are created and consumed by specific instructions or the hardware, the exact format of these words can change between hardware implementation and user programs do not need to be recompiled, since the same code stream will produce the same results, even though system word format may have changed.

Tag 1 words represent on-stack data addresses. The normal IRW simply stores an address couple to data on the current stack. The SIRW references data on any stack by including a stack number in the address.

Tag 5 words are descriptors, which are more fully described in the next section. Tag 5 words represent off-stack data addresses.

Tag 7 is the program control word which describes a procedure entry point. When operators hit a PCW, the procedure is entered. The ENTR operator explicitly enters a procedure (non-value-returning routine). Functions (value-returning routines) are implicitly entered by operators such as value call (VALC). Note that global routines are stored in the D[2] environment as SIRWs that point to a PCW stored in the code segment dictionary in the D[1] environment. The D[1] environment is not stored on the current stack because it can be referenced by all processes sharing this code. Thus code is reentrant and shared.

Tag 3 represents code words themselves, which won't occur on the stack. Tag 3 is also used for the stack control words MSCW, RCW, TOSCW.

[[Image:b6700Word.jpg|thumb|420px|left|Figure 9.2 From the ACM Monograph in the References. ''[[Elliot Organick]] 1973.'']]

==Descriptor-based architecture==

The figure to the left shows how the Burroughs Large System architecture was fundamentally a hardware architecture for [[Object-oriented programming]], something that still doesn't exist in conventional architectures.

{{Main|Burroughs large systems descriptors}}

==Instruction set==

{{Main|Burroughs large systems instruction set}}

==Multiple processors==
The B5000 line also were pioneers in having multiple processors connected together on a high-speed bus. The B7000 line could have up to 8 processors, as long as at least one was an IO module. Note that RDLK is a very low-level way of synchronizing between processors. The high level used by user programs is the EVENT data type. The EVENT data type did have some system overhead. To avoid this overhead, a special locking technique called Dahm locks (named after a Burroughs software guru, Dave Dahm) can be used.

Notable operators are:

'''HEYU''' — send an interrupt to another processor<br />
'''RDLK''' — Low-level semaphore operator: Load the A register with the memory location given by the A register and place the value in the B register at that memory location in a single uninterruptible cycle<br />
'''WHOI''' — Processor identification<br />
'''IDLE''' — Idle until an interrupt is received

Two processors could infrequently simultaneously send each other a 'HEYU' command resulting in a lockup known as 'a deadly embrace'.

==Influence of the B5000==
The direct influence of the B5000 can be seen in the current Unisys ClearPath range of mainframes which are the direct descendants of the B5000 and still have the MCP operating system after 40 years of consistent development. This architecture is now called emode (for emulation mode) since the B5000 architecture has been implemented on machines built from [[Intel Xeon]] processors running the [[x86]] instruction set as the native instruction set, with code running on those processors emulating the B5000 instruction set. In those machines, there was also going to be an nmode ([[native mode]]), but this was dropped{{Citation needed|date=September 2007}}, so you may often hear the B5000 successor machines being referred to as "emode machines".

B5000 machines were programmed exclusively in high-level languages; there is no assembler.

The B5000 stack architecture inspired [[Chuck Moore]], the designer of the programming language [[Forth (programming language)|Forth]], who encountered the B5500 while at MIT. In [http://www.colorforth.com/HOPL.html ''Forth - The Early Years''], Moore described the influence, noting that Forth's DUP, DROP and SWAP came from the corresponding B5500 instructions (DUPL, DLET, EXCH).

The [[Hewlett-Packard]] designers of the [[HP 3000]] business system had used a B5500 and were greatly impressed by its hardware and software; they aimed to build a 16-bit minicomputer with similar software. Several other HP divisions created similar minicomputer or microprocessor stack machines.  Bob Barton's work on [[reverse Polish notation]] (RPN) also found its way into [[HP calculators]] beginning with the 9100A, and notably the [[HP-35]] and subsequent calculators.

The NonStop systems designed by [[Tandem Computers]] in the late 1970s and early 1980s were also 16-bit stack machines, influenced by the B5000 indirectly through the HP 3000 connection, as several of the early Tandem engineers were formerly with HP.  Around 1990, these systems migrated to MIPS RISC architecture but continued to support execution of stack machine binaries by object code translation or direct emulation.  Sometime after 2000, these systems migrated to [[Itanium]] architecture and continued to run the legacy stack machine binaries.

Bob Barton was also very influential on [[Alan Kay]]. Kay was also impressed by the data-driven tagged architecture of the B5000 and this influenced his thinking in his developments in object-oriented programming and [[Smalltalk]].

Another facet of the B5000 architecture was that it was a secure architecture that runs directly on hardware. This technique has descendants in the virtual machines of today in their attempts to provide secure environments. One notable such product is the Java JVM which provides a secure sandbox in which applications run.

The value of the hardware-architecture binding that existed before emode would be substantially preserved in the [[x86]]-based machines to the extent that MCP was the one and only control program, but the support provided by those machines is still inferior to that provided on the machines where the B5000 instruction set is the native instruction set. A little-known Intel processor architecture that actually preceded x86, the [[Intel iAPX 432]], ''would'' have provided an equivalent physical basis, as it too was essentially an object oriented architecture.

== See also ==
* [[CANDE]]
* [[Work Flow Language|WFL]]

==Notes==
{{Reflist|group=NB}}

==References==
{{Refimprove|date=November 2009}}
* ''The Extended ALGOL Primer'' (Three Volumes), Donald J. Gregory.
* ''Computer Architecture: A Structured Approach,'' R. Doran, Academic Press (1979).
* ''Stack Computers: The New Wave,'' Philip J. Koopman, available at: [http://www.ece.cmu.edu/~koopman/stack_computers/index.html]
* B5500, B6500, B6700, B6800, B6900, B7700 manuals at: [http://www.bitsavers.org/pdf/burroughs/ bitsavers.org]
{{Reflist|refs=
<ref name=B5000-21005>
{{cite manual
 |     author = Burroughs
 |      title = The Operational Characteristics of the Processors for the Burroughs B5000
 |         id = 5000-21005
 |    version = Revision A
 |       date = 1963
 |        url = http://www.bitsavers.org/pdf/burroughs/B5000_5500_5700/5000-21005_B5000_operChar.pdf
 |  separator = ,
 }}</ref>

<ref name=B1021326>
{{cite manual
 |     author = Burroughs
 |      title = Burroughs B5500 Information Processing System Reference Manual
 |         id = 1021326
 |       date = May 1967
 |        url = http://www.bitsavers.org/pdf/burroughs/B5000_5500_5700/1021326_B5500_RefMan_May67.pdf
 |  separator = ,
 }}</ref>

<ref name=Da8500>
{{cite journal
 |     author = John T. Lynch
 |    journal = Datamation
 |      pages = 49–50
 |      title = The Burroughs B8500
 |       date = August 1965
 |        url = http://bitsavers.org/pdf/burroughs/B8500/B8500_Datamation_Aug65.pdf
 |  separator = ,
 }}</ref>

<ref name=Ga8500>
{{cite journal
 |     author = George Gray
 |    journal = Unisys History Newsletter
 |     volume = 3
 |      issue = 5
 |      title = Burroughs Third-Generation Computers
 |       date = October 1999
 |        url = https://wiki.cc.gatech.edu/folklore/index.php/Burroughs_Third-Generation_Computers
 |  separator = ,
 }}</ref>
}}

== Further reading ==
*Barton, Robert S. "A New Approach to the Functional Design of a Digital Computer" Proceedings of the Western Joint Computer Conference. ACM (1961).
*[http://www.cbi.umn.edu/oh/display.phtml?id=53 Burroughs B 5000 Oral history], [[Charles Babbage Institute]], University of Minnesota. The Burroughs 5000 computer series is discussed by individuals responsible for its development and marketing from 1957 through the 1960s in a 1985 conference sponsored by [[American Federation of Information Processing Societies|AFIPS]] and [[Burroughs Corporation]].
*Gray, George. [https://wiki.cc.gatech.edu/folklore/index.php/Some_Burroughs_Transistor_Computers "Some Burroughs Transistor Computers"], Unisys History Newsletter, Volume 3, Number 1, March 1999.
*Gray, George. [https://wiki.cc.gatech.edu/folklore/index.php/Burroughs_Third-Generation_Computers "Burroughs Third-Generation Computers], Unisys History Newsletter, Volume 3, Number 5, October 1999.
*Hauck, E.A., Dent, Ben A. "Burroughs B6500/B7500 Stack Mechanism", SJCC (1968) pp.&nbsp;245–251.
*McKeeman, William M. "Language Directed Computer Design", Fall Joint Computer Conference, (1967) pp.&nbsp;413–417.
*Organick, Elliot I. "Computer System Organization The B5700/B6700 series", Academic Press (1973)
* Waychoff, Richard, [http://web.me.com/ianjoyner/Files/Waychoff.pdf "Stories of the B5000 and People Who Were There"], September 27, 1979

== External links ==
*[http://web.me.com/ianjoyner/Ian_Joyner/Burroughs.html Ian Joyner's page on the Burroughs B5000]
*[http://jack.hoaroots.org/b5900.htm Jack Allweiss's ('Father of the B5900') site; shows evolution of the stack architecture over the models and many images of Burroughs models.]
*[http://users.monash.edu.au/~ralphk/burroughs.html Ralph Klimek on the B7800 at Monash University]
* [http://www.cs.virginia.edu/brochure/museum.html "Early Burroughs Machines"], University of Virginia's Computer Museum.
* [http://bitsavers.org/pdf/burroughs/B8500/ Index of B8500 manuals]
* [http://jack.hoaroots.org/BurrMain.html The Burroughs B5900 and E-Mode: A bridge to 21st Century Computing] - Jack Allweiss